1. Field of the Invention
The present invention relates to a voltage generation circuit used for a non-volatile semiconductor memory device. More specifically the invention pertains to a voltage generation circuit including a booster circuit to boost a power supply voltage and output boosted voltages corresponding to respective working modes.
2. Description of the Related Art
In semiconductor memory devices, read, program (write), and erase operations to each of memory cells, which are arranged in a matrix to construct a memory cell array, are implemented by specifying an address in both a row direction and a column direction.
A voltage applied to a signal line in the row direction and to a signal line in the column direction, which are connected with each memory cell, is regulated to gain access to a specified memory cell for a selected operation among the read, program, and erase operations. For selection of the specified memory cell, a voltage, which is different from the voltage applied to the other memory cells, is to be generated from a power supply voltage and to be applied to the specified memory cell.
MONOS (metal-oxide-nitride-oxide-semiconductor or -substrate) memory devices have been developed recently as non-volatile semiconductor memory devices that are electrically erasable. In such MONOS-type non-volatile semiconductor memory devices, each memory cell has two memory elements as discussed in detail in a cited reference Y. Hayashi et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, p122-p123.
As described in this cited reference, it is required to apply multiple voltages on signal lines (control lines) corresponding to the respective memory cells as control voltages, in order to gain access to the memory elements in the MONOS-type non-volatile semiconductor memory device via the respective signal lines (control lines). Various levels of control voltages are also required for respective working modes (read, program, erase, and standby) with regard to each memory element.
Such control voltages are generated by a voltage generation circuit. The voltage generation circuit typically includes a booster circuit that boosts a power supply voltage to voltages corresponding to the respective working modes, and a control voltage generation circuit that generates multiple control voltages from the boosted voltages in the respective working modes. The booster circuit boosts, for example, a power supply voltage of 1.8 V to a higher voltage of 8.0 V and outputs the higher voltage of 8.0 V in the program (write) mode or in the erase mode, while boosting the power supply voltage of 1.8 V to a lower voltage of 5.0 V and outputting the lower voltage of 5.0 V in the read mode or in the standby mode.
The excessively long program time or erase time to the non-volatile memory element undesirably makes the non-volatile memory element fall into an over program state or in an over erase state, which may result in malfunctions.
The technique to prevent the occurrence of the over program state or the over erase state divides a required time for the program operation or the erase operation to one non-volatile memory element into multiple short time intervals and carries out multiple program and erase operations. At each time of the program or erase operation, a read operation from the memory element as the target of the program or the erase operation is executed to verify the status of the program or the status of the erase. This read operation is called the xe2x80x98verifyxe2x80x99 operation. Multiple sets of the program and verify combination (hereafter referred to as the xe2x80x98program accessxe2x80x99) or the erase and verify combination (hereafter referred to as the xe2x80x98erase accessxe2x80x99) are repeated until completion of the program or erase operation to the memory element. The program access and the erase access are genetically called the xe2x80x98erase/program accessxe2x80x99.
In order to prevent the over program state or the over erase state and ensure the effective program access or the erase access, the preferable technique minimizes the erase/program access time and maximizes the executable number of erase/program accesses within a conventional erase/program access time.
The prior art voltage generation circuit including the booster circuit, however, has a problem discussed below.
FIG. 8 shows a problem of the booster circuit included in the prior art voltage generation circuit. The booster circuit switches over the output voltage between the lower voltage of 5.0 V corresponding to the read mode and the higher voltage of 8.0 V corresponding to the program mode or the erase mode. A charge pump is applied for the booster circuit. The charge pump iteratively accumulates the power supply voltage in response to clock signals and thereby outputs available boosted voltages. The charge pump generally has a poor response to the switchover of the output voltage. The booster circuit has a capacitor for voltage accumulation and a parasitic capacitor. Charge and discharge of electric charges into and from these capacitors worsen the response to the switchover of the output voltage generated by the booster circuit according to the working mode. The booster circuit thus generally requires a relatively long time to set a voltage corresponding to each working mode ready for output. For example, as shown in the graph of FIG. 8, the switchover time of the output in the booster circuit is approximately 1 xcexcs.
A relatively long time is accordingly required to make the verify operation executable after execution of a first program or erase operation. A relatively long time is also required to make a second program or erase operation executable after execution of the verify operation. This undesirably lengthens the time required to make the second program access or erase access executable after execution of the first program access or erase access.
In the illustrated example, each program or erase time is about 1 xcexcs, the verify time is about 300 ns, and the switchover time of the output in the booster circuit is about 1 xcexcs. The total erase/program access time is thus about 3.3 xcexcs. The executable number of erase/program accesses is thus only three times at the maximum within a conventional erase/program access time of approximately 10 xcexcs in the prior art non-volatile semiconductor memory devices.
The object of the present invention is thus to solve the problem of the prior art technique and to provide a voltage generation circuit for a non-volatile semiconductor memory device, which shortens each erase/program access time and thereby increases the executable number of erase/program accesses within a conventional erase/program access time.
In order to attain at least part of the above and the other related objects, the present invention is directed to a voltage generation circuit applied for a non-volatile semiconductor memory device, which has a memory cell array including multiple non-volatile memory elements. The non-volatile semiconductor memory device has plural working modes, that is, a program mode for writing into each of the multiple non-volatile memory elements, an erase mode for erasing from each of the multiple non-volatile memory elements, a verify mode for reading each of the multiple non-volatile memory elements to verify either of a status of the writing and a status of the erasing, and a read mode for reading from each of the multiple non-volatile memory elements.
The voltage generation circuit includes: a booster circuit having at least a first booster module that boosts a power supply voltage and outputs a first boosted voltage corresponding to either of the program mode and the erase mode, and a second booster module that boosts the power supply voltage and outputs a second boosted voltage, which is different from the first boosted voltage, corresponding to the verify mode; and a control voltage generation circuit that generates at least a voltage corresponding to the program mode, based on the first boosted voltage, in the program mode, a voltage corresponding to the erase mode, based on the first boosted voltage, in the erase mode, and a voltage corresponding to the verify mode, based on the second boosted voltage, in the verify mode, as control voltages to control operations of each of the multiple non-volatile memory elements.
The control voltage generation circuit included in the voltage generation circuit of the invention generates the voltage corresponding to either the program mode or the erase mode as the control voltage, based on the first boosted voltage output from the first booster module, in the program mode or in the erase mode. The control voltage generation circuit also generates the voltage corresponding to the verify mode as the control voltage, based on the second boosted voltage output from the second booster module, in the verify mode. This structure generates the control voltages in the respective working modes, based on the boosted voltages output from the different booster modules, that is, from the first booster module in the program mode or in the erase mode and from the second booster module in the verify mode. The arrangement enables the first booster module to be set ready for output of the first boosted voltage and the second booster module to be set ready for output of the second boosted voltage.
This structure effectively solves the problem of the prior art technique that requires a relatively long time to switch over the output voltage between the boosted voltage corresponding to the program mode or the erase mode and the boosted voltage corresponding to the verify mode. The arrangement thus desirably shortens each erase/program access time and increases the executable number of erase/program accesses within a conventional erase/program access time.
In one preferable embodiment of the voltage generation circuit of the invention, the booster circuit further includes a third booster module that boosts the power supply voltage and outputs a third boosted voltage corresponding to the read mode. The control voltage generation circuit generates a voltage corresponding to the read mode as the control voltage, based on the third boosted voltage, in the read mode.
In this preferable structure, the third booster module may be set ready to output the third boosted voltage corresponding to the read mode. At a start of the read mode, the voltage corresponding to the read mode can be generated within a short time period as a control voltage, based on the third boosted voltage set ready for output.
In one preferable application of the voltage generation circuit of the invention, the control voltage generation circuit generates a voltage corresponding to the read mode as the control voltage, based on the second boosted voltage, in the read mode.
In another preferable application of the voltage generation circuit of the invention, the first booster module outputs the first boosted voltage in either of the program mode and the erase mode, while outputting a third boosted voltage in the read mode. The control voltage generation circuit generates a voltage corresponding to the read mode as the control voltage, based on the third boosted voltage, in the read mode.
This arrangement reduces the required number of booster modules, thus desirably reducing the size and the power consumption of the whole memory device.
In one preferable embodiment of the invention, each of the first through third booster modules includes: an oscillation circuit that carries out an oscillating operation to output a clock signal; a charge pump circuit that boosts the power supply voltage and outputs the boosted voltage, in response to the clock signal from the oscillation circuit; and a level sense circuit that controls the oscillating operation of the oscillation circuit to make the boosted voltage output from the charge pump circuit equal to a setting voltage specified for each corresponding working mode.
This arrangement facilitates construction of the first through the third booster modules.
In the non-volatile semiconductor memory device, for which the voltage generation circuit of the invention is applied, each of the multiple non-volatile memory elements may be constructed as a twin memory cell that is controlled by one word gate and two control gates.
This structure allows for the operations in the multiple working modes, for example, in the program, the erase, the verify, and the read modes, with regard to the memory cell array including twin memory cells.
In the non-volatile semiconductor memory device, for which the voltage generation circuit of the invention is applied, each of the multiple non-volatile memory elements may have an ONO film that includes an oxide film (O), a nitride film (N), and an oxide film (O) and functions as a trap site of electric charge.
This structure enables control voltages to be generated in the non-volatile semiconductor memory device using MONOS non-volatile memory elements.
The present invention is not limited to the voltage generation circuit discussed above. Another application of the invention is a non-volatile semiconductor memory device including the voltage generation circuit.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment with the accompanying drawings.